Die-to-Die IP

– UCIe-A PHY

– UCIe-S PHY

– UCIe Adapter

– UCIe Protocols

– IP Evaluation Kit

Memory Interface IP

NAND Flash (ONFI)

– ONFI 3600 I/O & PHY

– ONFI 4800 I/O & PHY

– ONFI 6400 I/O & PHY

DDR / LPDDR

– DDR  PHY

– LPDDR  PHY

– DDR / LPDDR Combo PHY

Other IP

– MIPI PHY

– Custom I/O

– Optimized Standard Cells

Customization Services

– IP Customization Services

– IP Integration Services

Die-to-Die IP Family

InPsy’s die-to-die IP conforms to the latest UCIe specifications and is a state-of-the-art high speed interface for next-gen multi-die and chiplet architectures

  • IP Customization Services

    Every product is different and that’s why general-purpose UCIe IP almost always forces uncomfortable PPA tradeoffs – tradeoffs that shouldn’t be necessary given the tens to hundreds of millions of dollars it costs to bring a product to market. InPsy can custom craft the UCIe IP architecture to your exact performance, power, packaging, and reliability targets to avoid these compromises.  What’s your priority? Beachfront density, depth, metal-layer or MIM layer reduction, bit-error performance, power efficiency, latency, package type, or unique floorplan constraints?  We’ll co-engineer the IP with you to meet your precise specifications without suffering any of the tradeoffs.
    ‍
    Customization services also cover the ONFI IP portfolio.  A one-size-fits-all ONFI PHY or I/O macro accumulate limitations as data rates climb,  packaging constraints increase, and layout constraints multiply. InPsy’s ONFI customization service tailors the PHY architecture, DQ/DQS timing algorithms, driving strengths, termination options, training sequences, as well as the IOs to your specific NAND configuration and signal-integrity environment.  We optimize the IP for your die size, metal stack, energy efficiency, and system-level requirements to deliver an ONFI IP that is cleaner to integrate, features stronger margins, and meets your exact performance targets.

    InPsy’s IP Customization Service designs the IP to fit your product – never the other way around.

    Key Features

    • InPsy’s most in-demand engagement model
    • Maximizes PPA efficiency and enables design flexibility
    • Custom-crafted IP aligns with each system’s unique architecture
    • Combines systematic verification, stringent margin analysis, and milestone-based design reviews to guarantee design quality
    • IP delivered within 20-26 weeks with accelerated timelines for priority programs

  • IP Integration Services

    InPsy’s UCIe and ONFI IP Integration Services seamlessly incorporates each IP block into your SoC or chiplet and includes comprehensive cross-domain SI/PI analysis services. We collaborate with your engineering team to deliver smoother bring-up, faster schedules, and first-silicon success.

    The UCIe Integration Services co-optimizes PHY placement, beachfront planning, metal-stack usage, timing closure, protocol mapping (AXI, CXS, CHI-C2C, streaming), link-training behavior, SI/PI margin assessments, and 2.5D/3D packaging constraints to guarantee margin-rich and predictable die-to-die performance.

    The ONFI Integration Services can tailor the DQ/DQS timing, pad-ring and pin placement, driving strengths, termination schemes, power-grid and IR-drop alignment, and controller-interface so that high-speed NAND interfaces close timing cleanly and operate with robust PVT margins.

    Key Features

    • The pathway to first-silicon success
    • End-to-end integration ownership, ensures UCIe and ONFI IP drop cleanly into your SoC or chiplet
    • Minimal rework across analog, digital, and physical domains
    • Cross-domain co-engineering across timing, clocking, SI/PI, IR-drop, pad-ring placement, beachfront optimization, packaging routes (2.5D/3D), and power-domain alignment
    • Floorplan-to-silicon guidance, including metal-stack usage, routing constraints, congestion management, controller/PHY placement optimization, and package-aware parasitic analysis
    • System-level verification and bring-up support, covering protocol alignment, controller mapping, training/debug flow tuning, and coordinated test
    • Co-engineering integration reviews, milestone-based checkpoints, margin validation, corner-case stress testing, and verification

  • MIPI PHY

    This MIPI D-PHY/C-PHY solution adheres to the MIPI Alliance standards and supports scalable link distances, including short-reach, and long-reach modes. It delivers optimized signal integrity and power efficiency for advanced imaging and display pipelines.

    Key Features

    • Compliant with MIPI DSI and CSI standards
    • Supports C/D combo or D only PHY
    • Supports both Transmit and Receive PHY
    • D-PHY speed up to 4.5Gbps and C-PHY up to 3.5Gsps
    • Supports 1, 2 or 4 lanes PHY
    • Supports Automotive grades with high ESD protection

  • Custom I/O

    The custom IO solution includes GPIO, Over-Drive IO (ODIO), fail-safe IO, crystal interfaces IO, high-ESD protection Circuitry, and support for standard IO protocols such as RGMII, eMMC, and ONFI.  Can be custom crafted on request.

  • Optimized Standard Cells

    InPsy’s optimized standard cell library delivers exceptional PPA efficiency for customer specific designs on popular process nodes.  Variants are purpose-built for high-performance computing, AI workloads, and storage applications. Featuring tuned transistor architectures, multiple Vt options, and refined drive-strength granularity, the library enables higher frequencies, lower latency, and better power control.  Available in 6T, 9T, and 12T track-heights.

    Key Features

    • Commercially proven across multiple foundries / process nodes
    • Flexible Multi-Track Height Options
    • Advanced Circuit Architecture with Multi-Vt support
    • High-Performance Datapath and Clocking Cells
    • Comprehensive Corner Characterization and Low-Power Features
    • Can be custom-crafted upon request

  • DDR PHY

    InPsy’s DDR PHY solutions are engineered to deliver exceptional performance, power efficiency, and signal integrity across advanced process nodes, drawing on over 20 years of development and mass-production experience from our founding R&D team – who previously built multiple generations of leading-edge DDR PHY IP on the most advanced-node geometries of their time. Designed to support the demanding performance and timing requirements of modern high-speed DDR interfaces, InPsy’s PHY architectures use optimized transistor structures, multiple Vt device options, and precise drive-strength tuning to deliver strong signal integrity, stable timing margins, and excellent PPA efficiency. The underlying physical design balances density with robustness, ensuring that critical data and command paths maintain consistent performance across wide PVT conditions and at aggressive data rates. Combined with well-engineered I/O structures, reliable on-die termination, and proven calibration techniques, InPsy’s DDR PHY design methodology offers a solid, silicon-proven foundation for customers building next-generation DRAM subsystems with confidence.

    Key Features

    • Commercially proven and validated across multiple customer programs
    • Multi-Standard DDR Support: Featuring compliance with JEDEC standards for DDR3, DDR3L, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR4x, LPDDR5, and LPDDR5X, enabling versatile combinations across various markets
    • Flexible Configuration: Allowing customizable channel architectures with support for 1, 2, or 4 independent channels, along with configurable lane ordering to accommodate different DRAM package types
    • Advanced Performance Optimization: Delivering maximum data rates up to 8533 Mbps, ultra-fast training, and programmable PHY boundary timing for low latency and efficient operation
    • Dynamic Power Management: Integrating DVFS capabilities, power-saving modes, and multiple voltage domains to enhance energy efficiency while meeting diverse workload demands
    • Enhanced Calibration and Training: Utilizing firmware-based solutions for independent training, DRAM initialization, and robust data eye monitoring features to ensure reliable operation and effective performance tuning

  • LPDDR PHY

    InPsy’s LPDDR PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.

    Key Features

    • Supports up to 8,533 MT/s data rate, depending on process node
    • Compliant with JEDEC and LPDDR5X compliant
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • AMBA APB3.0 compliant
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)

  • DDR / LPDDR Combo PHY

    InPsy’s DDR and LPDDR Combo PHY supports multiple generations of DDR and LPDDR, providing flexibility, backward compatibility, and supply chain flexibility for HPC, mobile, and data centers applications. It ensures robust performance with high data rates, low latency, and efficient power consumption.

    Key Features

    • Multiple DDR/LPDDR interface combinations
    • JEDEC DDR and LPDDR compliant
    • Supports auto calibration
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)
    • AMBA APB3.0 compliant for register accessing

  • ONFI 3600 IO & PHY

    InPsy’s ONFI 3600 MT/s IP is a silicon-proven and widely validated NAND interface that meets the ONFI 5.1 specification. This IP is optimized with focus on tighter electrical, timing, and signal-integrity.  It incorporates refined equalization, robust training algorithms, and resilient PVT-tracking to ensure stable high-speed operation.  This is a deployment-ready option for SSD controllers, embedded storage subsystems, and other high-performance storage silicon and its proven track record offers predictable interoperability with a broad ecosystem of NAND devices.

    Key Features

    • Commercially-proven across multiple foundries and process nodes
    • Supports ONFI speed grades of 3600 MT/s
    • Multiple I/O drive strengths and termination schemes, including CTT and LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

  • ONFI 4800 IO & PHY

    InPsy’s ONFI 4800 IP is a next gen NAND interface architected with a forward-looking design philosophy that anticipates the key soon-to-be finalized ONFI 5.x specifications. The IP is ground-up engineered with the electrical, timing, and architectural requirements for next gen ONFI 5.x data-rate operation, tighter signal integrity expectations, enhanced command/address structures, and improved reliability features. It delivers a robust and future-proof solution to seamlessly transition to next-generation Flash devices when the 5.x standard is finalized. The ONFI 4800 IP has been validated in successful customer tape-outs, a real-world track record of low integration risk, and consistent interoperability across a range of NAND memory.

    Key Features

    • Commercially proven across multiple foundries and process nodes
    • Supports 4800 MT/s and can be boosted to 5500 MT/s
    • Supports 1-to-4 tap decision equalization feedback (DFE)
    • Multiple I/O drive strengths and termination schemes, including CTT, LTT, and PI-LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

Memory Interface & Storage IP

NAND Flash (ONFI)

  • IP Customization Services

    Every product is different and that’s why general-purpose UCIe IP almost always forces uncomfortable PPA tradeoffs – tradeoffs that shouldn’t be necessary given the tens to hundreds of millions of dollars it costs to bring a product to market. InPsy can custom craft the UCIe IP architecture to your exact performance, power, packaging, and reliability targets to avoid these compromises.  What’s your priority? Beachfront density, depth, metal-layer or MIM layer reduction, bit-error performance, power efficiency, latency, package type, or unique floorplan constraints?  We’ll co-engineer the IP with you to meet your precise specifications without suffering any of the tradeoffs.
    ‍
    Customization services also cover the ONFI IP portfolio.  A one-size-fits-all ONFI PHY or I/O macro accumulate limitations as data rates climb,  packaging constraints increase, and layout constraints multiply. InPsy’s ONFI customization service tailors the PHY architecture, DQ/DQS timing algorithms, driving strengths, termination options, training sequences, as well as the IOs to your specific NAND configuration and signal-integrity environment.  We optimize the IP for your die size, metal stack, energy efficiency, and system-level requirements to deliver an ONFI IP that is cleaner to integrate, features stronger margins, and meets your exact performance targets.

    InPsy’s IP Customization Service designs the IP to fit your product – never the other way around.

    Key Features

    • InPsy’s most in-demand engagement model
    • Maximizes PPA efficiency and enables design flexibility
    • Custom-crafted IP aligns with each system’s unique architecture
    • Combines systematic verification, stringent margin analysis, and milestone-based design reviews to guarantee design quality
    • IP delivered within 20-26 weeks with accelerated timelines for priority programs

  • IP Integration Services

    InPsy’s UCIe and ONFI IP Integration Services seamlessly incorporates each IP block into your SoC or chiplet and includes comprehensive cross-domain SI/PI analysis services. We collaborate with your engineering team to deliver smoother bring-up, faster schedules, and first-silicon success.

    The UCIe Integration Services co-optimizes PHY placement, beachfront planning, metal-stack usage, timing closure, protocol mapping (AXI, CXS, CHI-C2C, streaming), link-training behavior, SI/PI margin assessments, and 2.5D/3D packaging constraints to guarantee margin-rich and predictable die-to-die performance.

    The ONFI Integration Services can tailor the DQ/DQS timing, pad-ring and pin placement, driving strengths, termination schemes, power-grid and IR-drop alignment, and controller-interface so that high-speed NAND interfaces close timing cleanly and operate with robust PVT margins.

    Key Features

    • The pathway to first-silicon success
    • End-to-end integration ownership, ensures UCIe and ONFI IP drop cleanly into your SoC or chiplet
    • Minimal rework across analog, digital, and physical domains
    • Cross-domain co-engineering across timing, clocking, SI/PI, IR-drop, pad-ring placement, beachfront optimization, packaging routes (2.5D/3D), and power-domain alignment
    • Floorplan-to-silicon guidance, including metal-stack usage, routing constraints, congestion management, controller/PHY placement optimization, and package-aware parasitic analysis
    • System-level verification and bring-up support, covering protocol alignment, controller mapping, training/debug flow tuning, and coordinated test
    • Co-engineering integration reviews, milestone-based checkpoints, margin validation, corner-case stress testing, and verification

  • MIPI PHY

    This MIPI D-PHY/C-PHY solution adheres to the MIPI Alliance standards and supports scalable link distances, including short-reach, and long-reach modes. It delivers optimized signal integrity and power efficiency for advanced imaging and display pipelines.

    Key Features

    • Compliant with MIPI DSI and CSI standards
    • Supports C/D combo or D only PHY
    • Supports both Transmit and Receive PHY
    • D-PHY speed up to 4.5Gbps and C-PHY up to 3.5Gsps
    • Supports 1, 2 or 4 lanes PHY
    • Supports Automotive grades with high ESD protection

  • Custom I/O

    The custom IO solution includes GPIO, Over-Drive IO (ODIO), fail-safe IO, crystal interfaces IO, high-ESD protection Circuitry, and support for standard IO protocols such as RGMII, eMMC, and ONFI.  Can be custom crafted on request.

  • Optimized Standard Cells

    InPsy’s optimized standard cell library delivers exceptional PPA efficiency for customer specific designs on popular process nodes.  Variants are purpose-built for high-performance computing, AI workloads, and storage applications. Featuring tuned transistor architectures, multiple Vt options, and refined drive-strength granularity, the library enables higher frequencies, lower latency, and better power control.  Available in 6T, 9T, and 12T track-heights.

    Key Features

    • Commercially proven across multiple foundries / process nodes
    • Flexible Multi-Track Height Options
    • Advanced Circuit Architecture with Multi-Vt support
    • High-Performance Datapath and Clocking Cells
    • Comprehensive Corner Characterization and Low-Power Features
    • Can be custom-crafted upon request

  • DDR PHY

    InPsy’s DDR PHY solutions are engineered to deliver exceptional performance, power efficiency, and signal integrity across advanced process nodes, drawing on over 20 years of development and mass-production experience from our founding R&D team – who previously built multiple generations of leading-edge DDR PHY IP on the most advanced-node geometries of their time. Designed to support the demanding performance and timing requirements of modern high-speed DDR interfaces, InPsy’s PHY architectures use optimized transistor structures, multiple Vt device options, and precise drive-strength tuning to deliver strong signal integrity, stable timing margins, and excellent PPA efficiency. The underlying physical design balances density with robustness, ensuring that critical data and command paths maintain consistent performance across wide PVT conditions and at aggressive data rates. Combined with well-engineered I/O structures, reliable on-die termination, and proven calibration techniques, InPsy’s DDR PHY design methodology offers a solid, silicon-proven foundation for customers building next-generation DRAM subsystems with confidence.

    Key Features

    • Commercially proven and validated across multiple customer programs
    • Multi-Standard DDR Support: Featuring compliance with JEDEC standards for DDR3, DDR3L, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR4x, LPDDR5, and LPDDR5X, enabling versatile combinations across various markets
    • Flexible Configuration: Allowing customizable channel architectures with support for 1, 2, or 4 independent channels, along with configurable lane ordering to accommodate different DRAM package types
    • Advanced Performance Optimization: Delivering maximum data rates up to 8533 Mbps, ultra-fast training, and programmable PHY boundary timing for low latency and efficient operation
    • Dynamic Power Management: Integrating DVFS capabilities, power-saving modes, and multiple voltage domains to enhance energy efficiency while meeting diverse workload demands
    • Enhanced Calibration and Training: Utilizing firmware-based solutions for independent training, DRAM initialization, and robust data eye monitoring features to ensure reliable operation and effective performance tuning

  • LPDDR PHY

    InPsy’s LPDDR PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.

    Key Features

    • Supports up to 8,533 MT/s data rate, depending on process node
    • Compliant with JEDEC and LPDDR5X compliant
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • AMBA APB3.0 compliant
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)

  • DDR / LPDDR Combo PHY

    InPsy’s DDR and LPDDR Combo PHY supports multiple generations of DDR and LPDDR, providing flexibility, backward compatibility, and supply chain flexibility for HPC, mobile, and data centers applications. It ensures robust performance with high data rates, low latency, and efficient power consumption.

    Key Features

    • Multiple DDR/LPDDR interface combinations
    • JEDEC DDR and LPDDR compliant
    • Supports auto calibration
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)
    • AMBA APB3.0 compliant for register accessing

  • ONFI 3600 IO & PHY

    InPsy’s ONFI 3600 MT/s IP is a silicon-proven and widely validated NAND interface that meets the ONFI 5.1 specification. This IP is optimized with focus on tighter electrical, timing, and signal-integrity.  It incorporates refined equalization, robust training algorithms, and resilient PVT-tracking to ensure stable high-speed operation.  This is a deployment-ready option for SSD controllers, embedded storage subsystems, and other high-performance storage silicon and its proven track record offers predictable interoperability with a broad ecosystem of NAND devices.

    Key Features

    • Commercially-proven across multiple foundries and process nodes
    • Supports ONFI speed grades of 3600 MT/s
    • Multiple I/O drive strengths and termination schemes, including CTT and LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

  • ONFI 4800 IO & PHY

    InPsy’s ONFI 4800 IP is a next gen NAND interface architected with a forward-looking design philosophy that anticipates the key soon-to-be finalized ONFI 5.x specifications. The IP is ground-up engineered with the electrical, timing, and architectural requirements for next gen ONFI 5.x data-rate operation, tighter signal integrity expectations, enhanced command/address structures, and improved reliability features. It delivers a robust and future-proof solution to seamlessly transition to next-generation Flash devices when the 5.x standard is finalized. The ONFI 4800 IP has been validated in successful customer tape-outs, a real-world track record of low integration risk, and consistent interoperability across a range of NAND memory.

    Key Features

    • Commercially proven across multiple foundries and process nodes
    • Supports 4800 MT/s and can be boosted to 5500 MT/s
    • Supports 1-to-4 tap decision equalization feedback (DFE)
    • Multiple I/O drive strengths and termination schemes, including CTT, LTT, and PI-LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

DDR / LPDDR

  • IP Customization Services

    Every product is different and that’s why general-purpose UCIe IP almost always forces uncomfortable PPA tradeoffs – tradeoffs that shouldn’t be necessary given the tens to hundreds of millions of dollars it costs to bring a product to market. InPsy can custom craft the UCIe IP architecture to your exact performance, power, packaging, and reliability targets to avoid these compromises.  What’s your priority? Beachfront density, depth, metal-layer or MIM layer reduction, bit-error performance, power efficiency, latency, package type, or unique floorplan constraints?  We’ll co-engineer the IP with you to meet your precise specifications without suffering any of the tradeoffs.
    ‍
    Customization services also cover the ONFI IP portfolio.  A one-size-fits-all ONFI PHY or I/O macro accumulate limitations as data rates climb,  packaging constraints increase, and layout constraints multiply. InPsy’s ONFI customization service tailors the PHY architecture, DQ/DQS timing algorithms, driving strengths, termination options, training sequences, as well as the IOs to your specific NAND configuration and signal-integrity environment.  We optimize the IP for your die size, metal stack, energy efficiency, and system-level requirements to deliver an ONFI IP that is cleaner to integrate, features stronger margins, and meets your exact performance targets.

    InPsy’s IP Customization Service designs the IP to fit your product – never the other way around.

    Key Features

    • InPsy’s most in-demand engagement model
    • Maximizes PPA efficiency and enables design flexibility
    • Custom-crafted IP aligns with each system’s unique architecture
    • Combines systematic verification, stringent margin analysis, and milestone-based design reviews to guarantee design quality
    • IP delivered within 20-26 weeks with accelerated timelines for priority programs

  • IP Integration Services

    InPsy’s UCIe and ONFI IP Integration Services seamlessly incorporates each IP block into your SoC or chiplet and includes comprehensive cross-domain SI/PI analysis services. We collaborate with your engineering team to deliver smoother bring-up, faster schedules, and first-silicon success.

    The UCIe Integration Services co-optimizes PHY placement, beachfront planning, metal-stack usage, timing closure, protocol mapping (AXI, CXS, CHI-C2C, streaming), link-training behavior, SI/PI margin assessments, and 2.5D/3D packaging constraints to guarantee margin-rich and predictable die-to-die performance.

    The ONFI Integration Services can tailor the DQ/DQS timing, pad-ring and pin placement, driving strengths, termination schemes, power-grid and IR-drop alignment, and controller-interface so that high-speed NAND interfaces close timing cleanly and operate with robust PVT margins.

    Key Features

    • The pathway to first-silicon success
    • End-to-end integration ownership, ensures UCIe and ONFI IP drop cleanly into your SoC or chiplet
    • Minimal rework across analog, digital, and physical domains
    • Cross-domain co-engineering across timing, clocking, SI/PI, IR-drop, pad-ring placement, beachfront optimization, packaging routes (2.5D/3D), and power-domain alignment
    • Floorplan-to-silicon guidance, including metal-stack usage, routing constraints, congestion management, controller/PHY placement optimization, and package-aware parasitic analysis
    • System-level verification and bring-up support, covering protocol alignment, controller mapping, training/debug flow tuning, and coordinated test
    • Co-engineering integration reviews, milestone-based checkpoints, margin validation, corner-case stress testing, and verification

  • MIPI PHY

    This MIPI D-PHY/C-PHY solution adheres to the MIPI Alliance standards and supports scalable link distances, including short-reach, and long-reach modes. It delivers optimized signal integrity and power efficiency for advanced imaging and display pipelines.

    Key Features

    • Compliant with MIPI DSI and CSI standards
    • Supports C/D combo or D only PHY
    • Supports both Transmit and Receive PHY
    • D-PHY speed up to 4.5Gbps and C-PHY up to 3.5Gsps
    • Supports 1, 2 or 4 lanes PHY
    • Supports Automotive grades with high ESD protection

  • Custom I/O

    The custom IO solution includes GPIO, Over-Drive IO (ODIO), fail-safe IO, crystal interfaces IO, high-ESD protection Circuitry, and support for standard IO protocols such as RGMII, eMMC, and ONFI.  Can be custom crafted on request.

  • Optimized Standard Cells

    InPsy’s optimized standard cell library delivers exceptional PPA efficiency for customer specific designs on popular process nodes.  Variants are purpose-built for high-performance computing, AI workloads, and storage applications. Featuring tuned transistor architectures, multiple Vt options, and refined drive-strength granularity, the library enables higher frequencies, lower latency, and better power control.  Available in 6T, 9T, and 12T track-heights.

    Key Features

    • Commercially proven across multiple foundries / process nodes
    • Flexible Multi-Track Height Options
    • Advanced Circuit Architecture with Multi-Vt support
    • High-Performance Datapath and Clocking Cells
    • Comprehensive Corner Characterization and Low-Power Features
    • Can be custom-crafted upon request

  • DDR PHY

    InPsy’s DDR PHY solutions are engineered to deliver exceptional performance, power efficiency, and signal integrity across advanced process nodes, drawing on over 20 years of development and mass-production experience from our founding R&D team – who previously built multiple generations of leading-edge DDR PHY IP on the most advanced-node geometries of their time. Designed to support the demanding performance and timing requirements of modern high-speed DDR interfaces, InPsy’s PHY architectures use optimized transistor structures, multiple Vt device options, and precise drive-strength tuning to deliver strong signal integrity, stable timing margins, and excellent PPA efficiency. The underlying physical design balances density with robustness, ensuring that critical data and command paths maintain consistent performance across wide PVT conditions and at aggressive data rates. Combined with well-engineered I/O structures, reliable on-die termination, and proven calibration techniques, InPsy’s DDR PHY design methodology offers a solid, silicon-proven foundation for customers building next-generation DRAM subsystems with confidence.

    Key Features

    • Commercially proven and validated across multiple customer programs
    • Multi-Standard DDR Support: Featuring compliance with JEDEC standards for DDR3, DDR3L, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR4x, LPDDR5, and LPDDR5X, enabling versatile combinations across various markets
    • Flexible Configuration: Allowing customizable channel architectures with support for 1, 2, or 4 independent channels, along with configurable lane ordering to accommodate different DRAM package types
    • Advanced Performance Optimization: Delivering maximum data rates up to 8533 Mbps, ultra-fast training, and programmable PHY boundary timing for low latency and efficient operation
    • Dynamic Power Management: Integrating DVFS capabilities, power-saving modes, and multiple voltage domains to enhance energy efficiency while meeting diverse workload demands
    • Enhanced Calibration and Training: Utilizing firmware-based solutions for independent training, DRAM initialization, and robust data eye monitoring features to ensure reliable operation and effective performance tuning

  • LPDDR PHY

    InPsy’s LPDDR PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.

    Key Features

    • Supports up to 8,533 MT/s data rate, depending on process node
    • Compliant with JEDEC and LPDDR5X compliant
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • AMBA APB3.0 compliant
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)

  • DDR / LPDDR Combo PHY

    InPsy’s DDR and LPDDR Combo PHY supports multiple generations of DDR and LPDDR, providing flexibility, backward compatibility, and supply chain flexibility for HPC, mobile, and data centers applications. It ensures robust performance with high data rates, low latency, and efficient power consumption.

    Key Features

    • Multiple DDR/LPDDR interface combinations
    • JEDEC DDR and LPDDR compliant
    • Supports auto calibration
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)
    • AMBA APB3.0 compliant for register accessing

  • ONFI 3600 IO & PHY

    InPsy’s ONFI 3600 MT/s IP is a silicon-proven and widely validated NAND interface that meets the ONFI 5.1 specification. This IP is optimized with focus on tighter electrical, timing, and signal-integrity.  It incorporates refined equalization, robust training algorithms, and resilient PVT-tracking to ensure stable high-speed operation.  This is a deployment-ready option for SSD controllers, embedded storage subsystems, and other high-performance storage silicon and its proven track record offers predictable interoperability with a broad ecosystem of NAND devices.

    Key Features

    • Commercially-proven across multiple foundries and process nodes
    • Supports ONFI speed grades of 3600 MT/s
    • Multiple I/O drive strengths and termination schemes, including CTT and LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

  • ONFI 4800 IO & PHY

    InPsy’s ONFI 4800 IP is a next gen NAND interface architected with a forward-looking design philosophy that anticipates the key soon-to-be finalized ONFI 5.x specifications. The IP is ground-up engineered with the electrical, timing, and architectural requirements for next gen ONFI 5.x data-rate operation, tighter signal integrity expectations, enhanced command/address structures, and improved reliability features. It delivers a robust and future-proof solution to seamlessly transition to next-generation Flash devices when the 5.x standard is finalized. The ONFI 4800 IP has been validated in successful customer tape-outs, a real-world track record of low integration risk, and consistent interoperability across a range of NAND memory.

    Key Features

    • Commercially proven across multiple foundries and process nodes
    • Supports 4800 MT/s and can be boosted to 5500 MT/s
    • Supports 1-to-4 tap decision equalization feedback (DFE)
    • Multiple I/O drive strengths and termination schemes, including CTT, LTT, and PI-LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

Other IP

  • IP Customization Services

    Every product is different and that’s why general-purpose UCIe IP almost always forces uncomfortable PPA tradeoffs – tradeoffs that shouldn’t be necessary given the tens to hundreds of millions of dollars it costs to bring a product to market. InPsy can custom craft the UCIe IP architecture to your exact performance, power, packaging, and reliability targets to avoid these compromises.  What’s your priority? Beachfront density, depth, metal-layer or MIM layer reduction, bit-error performance, power efficiency, latency, package type, or unique floorplan constraints?  We’ll co-engineer the IP with you to meet your precise specifications without suffering any of the tradeoffs.
    ‍
    Customization services also cover the ONFI IP portfolio.  A one-size-fits-all ONFI PHY or I/O macro accumulate limitations as data rates climb,  packaging constraints increase, and layout constraints multiply. InPsy’s ONFI customization service tailors the PHY architecture, DQ/DQS timing algorithms, driving strengths, termination options, training sequences, as well as the IOs to your specific NAND configuration and signal-integrity environment.  We optimize the IP for your die size, metal stack, energy efficiency, and system-level requirements to deliver an ONFI IP that is cleaner to integrate, features stronger margins, and meets your exact performance targets.

    InPsy’s IP Customization Service designs the IP to fit your product – never the other way around.

    Key Features

    • InPsy’s most in-demand engagement model
    • Maximizes PPA efficiency and enables design flexibility
    • Custom-crafted IP aligns with each system’s unique architecture
    • Combines systematic verification, stringent margin analysis, and milestone-based design reviews to guarantee design quality
    • IP delivered within 20-26 weeks with accelerated timelines for priority programs

  • IP Integration Services

    InPsy’s UCIe and ONFI IP Integration Services seamlessly incorporates each IP block into your SoC or chiplet and includes comprehensive cross-domain SI/PI analysis services. We collaborate with your engineering team to deliver smoother bring-up, faster schedules, and first-silicon success.

    The UCIe Integration Services co-optimizes PHY placement, beachfront planning, metal-stack usage, timing closure, protocol mapping (AXI, CXS, CHI-C2C, streaming), link-training behavior, SI/PI margin assessments, and 2.5D/3D packaging constraints to guarantee margin-rich and predictable die-to-die performance.

    The ONFI Integration Services can tailor the DQ/DQS timing, pad-ring and pin placement, driving strengths, termination schemes, power-grid and IR-drop alignment, and controller-interface so that high-speed NAND interfaces close timing cleanly and operate with robust PVT margins.

    Key Features

    • The pathway to first-silicon success
    • End-to-end integration ownership, ensures UCIe and ONFI IP drop cleanly into your SoC or chiplet
    • Minimal rework across analog, digital, and physical domains
    • Cross-domain co-engineering across timing, clocking, SI/PI, IR-drop, pad-ring placement, beachfront optimization, packaging routes (2.5D/3D), and power-domain alignment
    • Floorplan-to-silicon guidance, including metal-stack usage, routing constraints, congestion management, controller/PHY placement optimization, and package-aware parasitic analysis
    • System-level verification and bring-up support, covering protocol alignment, controller mapping, training/debug flow tuning, and coordinated test
    • Co-engineering integration reviews, milestone-based checkpoints, margin validation, corner-case stress testing, and verification

  • MIPI PHY

    This MIPI D-PHY/C-PHY solution adheres to the MIPI Alliance standards and supports scalable link distances, including short-reach, and long-reach modes. It delivers optimized signal integrity and power efficiency for advanced imaging and display pipelines.

    Key Features

    • Compliant with MIPI DSI and CSI standards
    • Supports C/D combo or D only PHY
    • Supports both Transmit and Receive PHY
    • D-PHY speed up to 4.5Gbps and C-PHY up to 3.5Gsps
    • Supports 1, 2 or 4 lanes PHY
    • Supports Automotive grades with high ESD protection

  • Custom I/O

    The custom IO solution includes GPIO, Over-Drive IO (ODIO), fail-safe IO, crystal interfaces IO, high-ESD protection Circuitry, and support for standard IO protocols such as RGMII, eMMC, and ONFI.  Can be custom crafted on request.

  • Optimized Standard Cells

    InPsy’s optimized standard cell library delivers exceptional PPA efficiency for customer specific designs on popular process nodes.  Variants are purpose-built for high-performance computing, AI workloads, and storage applications. Featuring tuned transistor architectures, multiple Vt options, and refined drive-strength granularity, the library enables higher frequencies, lower latency, and better power control.  Available in 6T, 9T, and 12T track-heights.

    Key Features

    • Commercially proven across multiple foundries / process nodes
    • Flexible Multi-Track Height Options
    • Advanced Circuit Architecture with Multi-Vt support
    • High-Performance Datapath and Clocking Cells
    • Comprehensive Corner Characterization and Low-Power Features
    • Can be custom-crafted upon request

  • DDR PHY

    InPsy’s DDR PHY solutions are engineered to deliver exceptional performance, power efficiency, and signal integrity across advanced process nodes, drawing on over 20 years of development and mass-production experience from our founding R&D team – who previously built multiple generations of leading-edge DDR PHY IP on the most advanced-node geometries of their time. Designed to support the demanding performance and timing requirements of modern high-speed DDR interfaces, InPsy’s PHY architectures use optimized transistor structures, multiple Vt device options, and precise drive-strength tuning to deliver strong signal integrity, stable timing margins, and excellent PPA efficiency. The underlying physical design balances density with robustness, ensuring that critical data and command paths maintain consistent performance across wide PVT conditions and at aggressive data rates. Combined with well-engineered I/O structures, reliable on-die termination, and proven calibration techniques, InPsy’s DDR PHY design methodology offers a solid, silicon-proven foundation for customers building next-generation DRAM subsystems with confidence.

    Key Features

    • Commercially proven and validated across multiple customer programs
    • Multi-Standard DDR Support: Featuring compliance with JEDEC standards for DDR3, DDR3L, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR4x, LPDDR5, and LPDDR5X, enabling versatile combinations across various markets
    • Flexible Configuration: Allowing customizable channel architectures with support for 1, 2, or 4 independent channels, along with configurable lane ordering to accommodate different DRAM package types
    • Advanced Performance Optimization: Delivering maximum data rates up to 8533 Mbps, ultra-fast training, and programmable PHY boundary timing for low latency and efficient operation
    • Dynamic Power Management: Integrating DVFS capabilities, power-saving modes, and multiple voltage domains to enhance energy efficiency while meeting diverse workload demands
    • Enhanced Calibration and Training: Utilizing firmware-based solutions for independent training, DRAM initialization, and robust data eye monitoring features to ensure reliable operation and effective performance tuning

  • LPDDR PHY

    InPsy’s LPDDR PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.

    Key Features

    • Supports up to 8,533 MT/s data rate, depending on process node
    • Compliant with JEDEC and LPDDR5X compliant
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • AMBA APB3.0 compliant
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)

  • DDR / LPDDR Combo PHY

    InPsy’s DDR and LPDDR Combo PHY supports multiple generations of DDR and LPDDR, providing flexibility, backward compatibility, and supply chain flexibility for HPC, mobile, and data centers applications. It ensures robust performance with high data rates, low latency, and efficient power consumption.

    Key Features

    • Multiple DDR/LPDDR interface combinations
    • JEDEC DDR and LPDDR compliant
    • Supports auto calibration
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)
    • AMBA APB3.0 compliant for register accessing

  • ONFI 3600 IO & PHY

    InPsy’s ONFI 3600 MT/s IP is a silicon-proven and widely validated NAND interface that meets the ONFI 5.1 specification. This IP is optimized with focus on tighter electrical, timing, and signal-integrity.  It incorporates refined equalization, robust training algorithms, and resilient PVT-tracking to ensure stable high-speed operation.  This is a deployment-ready option for SSD controllers, embedded storage subsystems, and other high-performance storage silicon and its proven track record offers predictable interoperability with a broad ecosystem of NAND devices.

    Key Features

    • Commercially-proven across multiple foundries and process nodes
    • Supports ONFI speed grades of 3600 MT/s
    • Multiple I/O drive strengths and termination schemes, including CTT and LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

  • ONFI 4800 IO & PHY

    InPsy’s ONFI 4800 IP is a next gen NAND interface architected with a forward-looking design philosophy that anticipates the key soon-to-be finalized ONFI 5.x specifications. The IP is ground-up engineered with the electrical, timing, and architectural requirements for next gen ONFI 5.x data-rate operation, tighter signal integrity expectations, enhanced command/address structures, and improved reliability features. It delivers a robust and future-proof solution to seamlessly transition to next-generation Flash devices when the 5.x standard is finalized. The ONFI 4800 IP has been validated in successful customer tape-outs, a real-world track record of low integration risk, and consistent interoperability across a range of NAND memory.

    Key Features

    • Commercially proven across multiple foundries and process nodes
    • Supports 4800 MT/s and can be boosted to 5500 MT/s
    • Supports 1-to-4 tap decision equalization feedback (DFE)
    • Multiple I/O drive strengths and termination schemes, including CTT, LTT, and PI-LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

Customization Services

  • IP Customization Services

    Every product is different and that’s why general-purpose UCIe IP almost always forces uncomfortable PPA tradeoffs – tradeoffs that shouldn’t be necessary given the tens to hundreds of millions of dollars it costs to bring a product to market. InPsy can custom craft the UCIe IP architecture to your exact performance, power, packaging, and reliability targets to avoid these compromises.  What’s your priority? Beachfront density, depth, metal-layer or MIM layer reduction, bit-error performance, power efficiency, latency, package type, or unique floorplan constraints?  We’ll co-engineer the IP with you to meet your precise specifications without suffering any of the tradeoffs.
    ‍
    Customization services also cover the ONFI IP portfolio.  A one-size-fits-all ONFI PHY or I/O macro accumulate limitations as data rates climb,  packaging constraints increase, and layout constraints multiply. InPsy’s ONFI customization service tailors the PHY architecture, DQ/DQS timing algorithms, driving strengths, termination options, training sequences, as well as the IOs to your specific NAND configuration and signal-integrity environment.  We optimize the IP for your die size, metal stack, energy efficiency, and system-level requirements to deliver an ONFI IP that is cleaner to integrate, features stronger margins, and meets your exact performance targets.

    InPsy’s IP Customization Service designs the IP to fit your product – never the other way around.

    Key Features

    • InPsy’s most in-demand engagement model
    • Maximizes PPA efficiency and enables design flexibility
    • Custom-crafted IP aligns with each system’s unique architecture
    • Combines systematic verification, stringent margin analysis, and milestone-based design reviews to guarantee design quality
    • IP delivered within 20-26 weeks with accelerated timelines for priority programs

  • IP Integration Services

    InPsy’s UCIe and ONFI IP Integration Services seamlessly incorporates each IP block into your SoC or chiplet and includes comprehensive cross-domain SI/PI analysis services. We collaborate with your engineering team to deliver smoother bring-up, faster schedules, and first-silicon success.

    The UCIe Integration Services co-optimizes PHY placement, beachfront planning, metal-stack usage, timing closure, protocol mapping (AXI, CXS, CHI-C2C, streaming), link-training behavior, SI/PI margin assessments, and 2.5D/3D packaging constraints to guarantee margin-rich and predictable die-to-die performance.

    The ONFI Integration Services can tailor the DQ/DQS timing, pad-ring and pin placement, driving strengths, termination schemes, power-grid and IR-drop alignment, and controller-interface so that high-speed NAND interfaces close timing cleanly and operate with robust PVT margins.

    Key Features

    • The pathway to first-silicon success
    • End-to-end integration ownership, ensures UCIe and ONFI IP drop cleanly into your SoC or chiplet
    • Minimal rework across analog, digital, and physical domains
    • Cross-domain co-engineering across timing, clocking, SI/PI, IR-drop, pad-ring placement, beachfront optimization, packaging routes (2.5D/3D), and power-domain alignment
    • Floorplan-to-silicon guidance, including metal-stack usage, routing constraints, congestion management, controller/PHY placement optimization, and package-aware parasitic analysis
    • System-level verification and bring-up support, covering protocol alignment, controller mapping, training/debug flow tuning, and coordinated test
    • Co-engineering integration reviews, milestone-based checkpoints, margin validation, corner-case stress testing, and verification

  • MIPI PHY

    This MIPI D-PHY/C-PHY solution adheres to the MIPI Alliance standards and supports scalable link distances, including short-reach, and long-reach modes. It delivers optimized signal integrity and power efficiency for advanced imaging and display pipelines.

    Key Features

    • Compliant with MIPI DSI and CSI standards
    • Supports C/D combo or D only PHY
    • Supports both Transmit and Receive PHY
    • D-PHY speed up to 4.5Gbps and C-PHY up to 3.5Gsps
    • Supports 1, 2 or 4 lanes PHY
    • Supports Automotive grades with high ESD protection

  • Custom I/O

    The custom IO solution includes GPIO, Over-Drive IO (ODIO), fail-safe IO, crystal interfaces IO, high-ESD protection Circuitry, and support for standard IO protocols such as RGMII, eMMC, and ONFI.  Can be custom crafted on request.

  • Optimized Standard Cells

    InPsy’s optimized standard cell library delivers exceptional PPA efficiency for customer specific designs on popular process nodes.  Variants are purpose-built for high-performance computing, AI workloads, and storage applications. Featuring tuned transistor architectures, multiple Vt options, and refined drive-strength granularity, the library enables higher frequencies, lower latency, and better power control.  Available in 6T, 9T, and 12T track-heights.

    Key Features

    • Commercially proven across multiple foundries / process nodes
    • Flexible Multi-Track Height Options
    • Advanced Circuit Architecture with Multi-Vt support
    • High-Performance Datapath and Clocking Cells
    • Comprehensive Corner Characterization and Low-Power Features
    • Can be custom-crafted upon request

  • DDR PHY

    InPsy’s DDR PHY solutions are engineered to deliver exceptional performance, power efficiency, and signal integrity across advanced process nodes, drawing on over 20 years of development and mass-production experience from our founding R&D team – who previously built multiple generations of leading-edge DDR PHY IP on the most advanced-node geometries of their time. Designed to support the demanding performance and timing requirements of modern high-speed DDR interfaces, InPsy’s PHY architectures use optimized transistor structures, multiple Vt device options, and precise drive-strength tuning to deliver strong signal integrity, stable timing margins, and excellent PPA efficiency. The underlying physical design balances density with robustness, ensuring that critical data and command paths maintain consistent performance across wide PVT conditions and at aggressive data rates. Combined with well-engineered I/O structures, reliable on-die termination, and proven calibration techniques, InPsy’s DDR PHY design methodology offers a solid, silicon-proven foundation for customers building next-generation DRAM subsystems with confidence.

    Key Features

    • Commercially proven and validated across multiple customer programs
    • Multi-Standard DDR Support: Featuring compliance with JEDEC standards for DDR3, DDR3L, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR4x, LPDDR5, and LPDDR5X, enabling versatile combinations across various markets
    • Flexible Configuration: Allowing customizable channel architectures with support for 1, 2, or 4 independent channels, along with configurable lane ordering to accommodate different DRAM package types
    • Advanced Performance Optimization: Delivering maximum data rates up to 8533 Mbps, ultra-fast training, and programmable PHY boundary timing for low latency and efficient operation
    • Dynamic Power Management: Integrating DVFS capabilities, power-saving modes, and multiple voltage domains to enhance energy efficiency while meeting diverse workload demands
    • Enhanced Calibration and Training: Utilizing firmware-based solutions for independent training, DRAM initialization, and robust data eye monitoring features to ensure reliable operation and effective performance tuning

  • LPDDR PHY

    InPsy’s LPDDR PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.

    Key Features

    • Supports up to 8,533 MT/s data rate, depending on process node
    • Compliant with JEDEC and LPDDR5X compliant
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • AMBA APB3.0 compliant
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)

  • DDR / LPDDR Combo PHY

    InPsy’s DDR and LPDDR Combo PHY supports multiple generations of DDR and LPDDR, providing flexibility, backward compatibility, and supply chain flexibility for HPC, mobile, and data centers applications. It ensures robust performance with high data rates, low latency, and efficient power consumption.

    Key Features

    • Multiple DDR/LPDDR interface combinations
    • JEDEC DDR and LPDDR compliant
    • Supports auto calibration
    • Supports DDR/LPDDR I/O with power-down retention
    • Supports CA and DQ signal swap table
    • Supports LPDDR dynamic voltage and frequency scaling (DVFS)
    • AMBA APB3.0 compliant for register accessing

  • ONFI 3600 IO & PHY

    InPsy’s ONFI 3600 MT/s IP is a silicon-proven and widely validated NAND interface that meets the ONFI 5.1 specification. This IP is optimized with focus on tighter electrical, timing, and signal-integrity.  It incorporates refined equalization, robust training algorithms, and resilient PVT-tracking to ensure stable high-speed operation.  This is a deployment-ready option for SSD controllers, embedded storage subsystems, and other high-performance storage silicon and its proven track record offers predictable interoperability with a broad ecosystem of NAND devices.

    Key Features

    • Commercially-proven across multiple foundries and process nodes
    • Supports ONFI speed grades of 3600 MT/s
    • Multiple I/O drive strengths and termination schemes, including CTT and LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

  • ONFI 4800 IO & PHY

    InPsy’s ONFI 4800 IP is a next gen NAND interface architected with a forward-looking design philosophy that anticipates the key soon-to-be finalized ONFI 5.x specifications. The IP is ground-up engineered with the electrical, timing, and architectural requirements for next gen ONFI 5.x data-rate operation, tighter signal integrity expectations, enhanced command/address structures, and improved reliability features. It delivers a robust and future-proof solution to seamlessly transition to next-generation Flash devices when the 5.x standard is finalized. The ONFI 4800 IP has been validated in successful customer tape-outs, a real-world track record of low integration risk, and consistent interoperability across a range of NAND memory.

    Key Features

    • Commercially proven across multiple foundries and process nodes
    • Supports 4800 MT/s and can be boosted to 5500 MT/s
    • Supports 1-to-4 tap decision equalization feedback (DFE)
    • Multiple I/O drive strengths and termination schemes, including CTT, LTT, and PI-LTT
    • Supports NV-DDR3 and NV-LPDDR4 flash @ 1.2V
    • Separate Command Address (SCA) significantly improves NAND interface efficiency
    • Miniature internal MCU unlocks post-silicon adaptability and feature scalability through firmware updates

Learn more about how we can customize a solution for you.

Contact Us